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timing controller for ccd camera description the CXD2463R generates the sync signals for timing control and back end signal processing in a ccd camera system using a 510h or 760h black- and-white ccd image sensor. features built-in sync signal generation function built-in electronic iris (electronic shutter) function supports low-speed limiter for electronic iris supports external synchronization (line-lock, vreset + hpll) supports automatic external sync discrimination window pulse output for backlight compensation built-in v driver applications surveillance camera door phone camera structure silicon gate cmos ic applicable ccd image sensors type 1/2, 760h black-and-white ccd (eia/ccir) type 1/3, 510/760h black-and-white ccd (eia/ccir) type 1/4, 510/760h black-and-white ccd (eia/ccir) absolute maximum ratings supply voltage v dd , av dd v ss ?0.5 to v ss + 7.0 v supply voltage v ss vl ?0.5 to vl + 26.0 v supply voltage vh vl ?0.5 to vl + 26.0 v supply voltage vm vl ?0.5 to vl + 26.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage 1 v dd , av dd 4.75 to 5.25 v supply voltage 3 vh 14.55 to 15.45 v supply voltage 4 vl ?.0 to ?.0 v supply voltage 5 vm 0 v operating temperature topr ?0 to +75 ? base oscillation 1212f h (eia: 19.0699mhz) (ccir: 18.9375mhz) 1820f h (eia: 28.6364mhz) 1816f h (ccir: 28.375mhz) ?1 e98930d18 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2463R 48 pin lqfp (plastic)
?2 CXD2463R no signal detection circuit vd detection circuit sync discrimination circuit gate hv-pll selector lcin comp evd ehd/sync ext hvdet vd hd eia v dd 1 v dd 2 v ss 1 v ss 2 test lcout cki ccd av ss h1 h2 av dd rg shp shd v1 v2 v3 v4 vl vm sub vh sync cblk clp1 clp2 blc blcw2 blcw1 cv ss irin/ed1 spdnv/ed2 vreg cv dd spupv/ed0 1/2 1/606 1/910 1/908 tg/ssg reset gen iris/shutter ck gen counter eshut2 eshut1 rst test circuit selector decode up/down adder gate vd ihd ivd eia hd 40 39 41 42 28 47 45 46 44 48 31 30 6 3 4 2 8 1 7 5 25 26 23 24 15 17 18 12 13 11 10 9 20 21 29 22 32 16 43 19 27 36 35 33 34 38 37 14 1/525 1/625 sync sep v driver decoder hv-pll selector block diagram
3 CXD2463R pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 irin/ed1 cv ss blc v ss 1 blcw1 blcw2 v dd 1 eshut2 eshut1 test clp1 clp2 sync cblk eia ccd rst shd shp v ss 2 hvdet ext vd hd spdnv/ed2 spupv/ed0 vreg cv dd vl sub v1 vh v3 v2 v4 vm rg av ss h2 h1 av dd v dd 2 cki lcout lcin comp ehd/sync evd pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vm v4 v2 v3 vh v1 sub vl cv dd vreg spupv/ed0 spdnv/ed2 irin/ed1 cv ss o o o o o i i i power supply (gnd for v driver) pulse output for ccd vertical register drive pulse output for ccd vertical register drive pulse output for ccd vertical register drive power supply (positive power supply for v driver) pulse output for ccd vertical register drive ccd discharge pulse output power supply (negative power supply for v driver) power supply (for comparator) bias current supply for comparator shutter speed up reference voltage/shutter speed setting shutter speed down reference voltage/shutter speed setting iris signal input/shutter speed setting gnd (for comparator) symbol i/o description
4 CXD2463R pin no. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 blc v ss 1 blcw1 blcw2 v dd 1 eshut2 eshut1 test clp1 clp2 sync cblk eia ccd rst shd shp v ss 2 hvdet ext vd hd evd ehd/sync comp lcin lcout cki v dd 2 av dd h1 h2 av ss rg o i i i i i o o o o i i i o o o o o o i i o i o i o o o window pulse output for backlight compensation gnd window select 1 for backlight compensation (with pull-down resistor) window select 2 for backlight compensation (with pull-down resistor) power supply sub pulse control (with pull-down resistor) sub pulse control (with pull-down resistor) fixed low (with pull-down resistor) clamp pulse output clamp pulse output composite sync output composite blanking output low: eia, high: ccir (with pull-down resistor) low: 510h, high: 760h (with pull-down resistor) reset (low reset). always input reset pulse after power-on. data sample-and-hold pulse precharge level sample-and-hold pulse gnd horizontal pll/vertical pll discrimination signal high: vertical pll, low: horizontal pll external sync/internal sync discrimination signal high: external sync, low: internal sync vertical drive output horizontal drive output vertical drive signal input (with pull-up resistor) horizontal drive signal input/composite sync input (with pull-up resistor) comparator output inverter input for oscillation inverter output for oscillation 2mck input power supply power supply (for h1, h2, and rg) h1 clock output for ccd horizontal register drive h2 clock output for ccd horizontal register drive gnd (for h1, h2, and rg) reset gate pulse output symbol i/o description
5 CXD2463R electrical characteristics 1) dc characteristics (v dd = 5v 0.25v, topr = 20 to +75 c) item v dd v ih 1 v il 1 v ih 2 v il 2 v in 3 v in 4 v oh 1 v ol 1 v oh 2 v ol 2 v oh 3 v ol 3 v oh 4 v ol 4 v oh 5 v ol 5 v oh 6 v ol 6 v oh 7 v ol 7 r fe 1 r fe 2 r pu r rd i vm i vl i vh i oh = 4.0ma i ol = 8.0ma i oh = 6.9ma i ol = 3.0ma i oh = 17.4ma i ol = 12.0ma i oh = 6.0ma i ol = 4.0ma i oh = 5.0ma i ol = 10.0ma i oh = 7.2ma i ol = 5.0ma i oh = 4.0ma i ol = 5.4ma v in = v dd or v ss v in = v dd or v ss v il = 0v v ih = v dd av dd = 5v cv dd = 5v v dd 1 = 5v v dd 2 = 5v v l = 8.5v v h = 15v 4.75 0.7v dd 0.8v dd 2.0 v ss v dd 0.8 v dd 0.8 v dd 0.8 v dd 0.8 v m 0.25 v h 0.25 v h 0.25 250k 250k 20k 20k 5.0 1m 1m 50k 50k 24 1.9 0.8 5.25 0.3v dd 0.2v dd v dd v dd 0.4 0.4 0.4 0.4 v l + 0.25 v m + 0.25 v l + 0 .25 2.5m 2.5m 125k 125k v v v v v v v v v v v v v v v v v v v v v ? ? ? ? ma ma ma symbol conditions min. typ. max. unit supply voltage input voltage 1 (for input pins not listed below) input voltage 2 (pin 29) input voltage 3 (pins 11 and 12 in electronic iris mode) input voltage 4 (pin 13 in electronic iris mode) output voltage 1 (pins 15, 23, 24, 25, 26, 33, 34, 35 and 36) output voltage 2 (pins 30, 31 and 48) output voltage 3 (pins 45 and 46) output voltage 4 (pin 39) output voltage 5 (pins 2, 3, 4 and 6) output voltage 6 (pins 4 and 6 (sg)) output voltage 7 (pin 7) feedback resistor 1 (pin 42) feedback resistor 2 (resistor between pins 40 and 41) pull-up resistor pull-down resistor current consumption ? the typical power consumption is 148mw with the icx054bl load (in the normal operating state).
6 CXD2463R 2) input/output capacitance (v dd = v i = 0v, f m = 1mhz) item input pin capacitance output pin capacitance i/o pin capacitance c in c out c i/o 9 11 11 pf pf pf symbol min. typ. max. unit 3) comparator characteristics (v dd = 5v 0.25v, topr = 20 to +75 c) item indefinite region vf 70 mv symbol min. typ. max. unit 4) power-on reset condition (within the recommended operating condition) item power-on reset period t wrst 35 ns symbol min. typ. max. unit note 1) input offset voltage and indefinite region the input offset voltage and indefinite region (region in which the comparator output is not set to high or low) shown in the figure below exist in the built-in comparator in this ic, so be careful when designing the external circuit. note 2) pins 11 and 12 in electronic iris mode make sure of pin 11 (spupv) < pin 12 (spdnv). 5.0v gnd 70mv 70mv pins 11 and 12 (spupv, spdnv) indefinite region 4.75v t wrst 0.2v dd v dd rst
7 CXD2463R 1. electronic iris/electronic shutter function the electronic iris or electronic shutter can be selected by setting the following pins to different combinations of high and low. eshut1 pin 21 l h l h l l h h electronic iris without limiter electronic iris with limiter eia: 1/100 (s), ccir: 1/120 (s) electronic shutter mode sub pulse stopped eshut2 pin 20 operating mode symbol irin/ed1 spdnv/ed2 spupv/ed0 13 12 11 iris signal input shutter speed down reference voltage shutter speed up reference voltage pin no. function 1) electronic iris mode symbol spupv/ed0 irin/ed1 spdnv/ed2 shutter speed 11 13 12 h h h eia: 1/100 ccir: 1/120 l h h 1/250 h l h 1/500 l l h 1/1000 h h l 1/2000 l h l 1/5000 h l l 1/10000 l l l 1/100000 pin no. mode 2) electronic shutter mode
8 CXD2463R 2. backlighting correction function the CXD2463R has a function to output the window pulse for backlight compensation. the backlight compensation pulse is output from blc (pin 15) in the following range according to the high/low combination of blcw1 (pin 17) and blcw2 (pin 18). window type for different pin combinations window type full-screen photometry bottom emphasis photometry center emphasis photometry bottom + center emphasis photometry l h l h l l h h blcw1 (pin 17) blcw2 (pin 18) example of basic circuit configuration iris comparator iris window switch agc window switch irin/ed1 13 blc 3.9k 10k 39k +5v 100k 10 iris op+ detout 1k 10k 100k 10 10k 10k CXD2463R cxa1310aq 15 27 19 13 full-screen photometry center emphasis photometry bottom emphasis photometry bottom + center emphasis photometry
9 CXD2463R 1) window pulse timing charts ?eia mode/vertical direction timing (1) full-screen photometry vd hd blc 20hd 20.5hd 0.5hd (2) center emphasis photometry vd hd blc 181hd 101hd 181.5hd 101.5hd (3) bottom emphasis photometry vd hd blc 181hd 181.5hd 0.5hd
10 CXD2463R ?eia mode/horizontal direction timing (1) bottom emphasis photometry and full-screen photometry hd mck blc x1 x2 x1 510h 760h 510h 760h 104mck 154mck 3mck 22mck x2 (2) center emphasis photometry hd mck blc x1 x2 x1 510h 760h 510h 760h 272mck 407mck 167mck 252mck x2
11 CXD2463R ?ccir mode/vertical direction timing (1) full-screen photometry vd hd blc 25hd 25.5hd 0.5hd (2) center emphasis photometry vd hd blc 216hd 121hd 216.5hd 121.5hd (3) bottom emphasis photometry vd hd blc 216hd 216.5hd 0.5hd
12 CXD2463R ?ccir mode/horizontal direction timing (1) bottom emphasis photometry and full-screen photometry hd mck blc x1 x2 x1 510h 760h 510h 760h 114mck 169mck 3mck 22mck x2 (2) center emphasis photometry hd mck blc x1 x2 x1 510h 760h 510h 760h 279mck 416mck 164mck 246mck x2
13 CXD2463R 3. external sync function the CXD2463R supports the three modes of line-lock, vreset + hpll (vd and hd inputs), and vreset + hpll (sync input) as the external sync functions. each mode is automatically switched according to the combination of signals input to ehd/sync (pin 38) and evd (pin 37). 1) automatic external sync discrimination i/o i i o o ehd/sync evd hvdet ext 38 37 33 34 hd no signal l l int no signal vd h h ll hd vd l h vreset + hpll sync hd after sync separation l h vreset + hpll no signal no signal l l int symbol pin no. ehd/sync and evd pins signal input state and hvdet and ext pins discrimination results mode if unspecified signals are input for the external signals given above, there may be recognition errors. 2) ll (line-lock) mode when the v sync clock is externally input to evd (pin 37), the result of comparing the falling edge of the clock and the falling edge of the internal vd is output from comp (pin 39). the output polarity is compatible with the active filter. ext-vd (pin 37) int-vd (pin 35) comp (pin 39) high impedance state
14 CXD2463R 3) vreset + hpll (vd and hd inputs) mode when the hd cycle clock is externally input to ehd/sync (pin 38) and the v cycle clock is externally input to the evd (pin 37), the CXD2463R sync signal is output as shown below based on the phase difference between these signals. similar to line-lock mode, the result of comparing the phase of the falling edges of the hd cycle clock input to pin 38 and the CXD2463R internal hd is output from comp (pin 39). the pll is applied using this signal. similar to line-lock mode, the polarity of the comp (pin 39) output is compatible with the active filter. the phase of the hd falling edge can be shifted up to 1/4h with respect to the falling edge of the master vd (ext- vd). ?eia/odd (1) ext-vd and ext-hd have the same phase. 1/4h 1/4h ext-vd (pin 37 input) ext-hd (pin 38 input) vd (pin 35 output) hd (pin 36 output) sync (pin 25 output) (2) ext-vd and ext-hd have the same phase to +1/4h. ext-vd ext-hd vd hd sync (3) ext-vd and ext-hd have the ?/4h to the same phase. ext-vd ext-hd vd hd sync
15 CXD2463R ?eia/even (1) ext-vd and ext-hd have the same phase. 1/4h 1/4h ext-vd (pin 37 input) ext-hd (pin 38 input) vd (pin 35 output) hd (pin 36 output) sync (pin 25 output) (2) ext-vd and ext-hd have the same phase to +1/4h. ext-vd ext-hd vd hd sync (3) ext-vd and ext-hd have the same phase to ?/4h. ext-vd ext-hd vd hd sync
16 CXD2463R ?ccir/odd (1) ext-vd and ext-hd have the same phase. 1/4h 1/4h ext-vd (pin 37 input) ext-hd (pin 38 input) vd (pin 35 output) hd (pin 36 output) sync (pin 25 output) (2) ext-vd and ext-hd have the same phase to +1/4h. ext-vd ext-hd vd hd sync (3) ext-vd and ext-hd have the same phase to ?/4h. ext-vd ext-hd vd hd sync
17 CXD2463R ?ccir/even (1) ext-vd and ext-hd have the same phase. 1/4h 1/4h ext-vd (pin 37 input) ext-hd (pin 38 input) vd (pin 35 output) hd (pin 36 output) sync (pin 25 output) (2) ext-vd and ext-hd have the same phase to +1/4h. ext-vd ext-hd vd hd sync (3) ext-vd and ext-hd have the same phase to ?/4h. ext-vd ext-hd vd hd sync
18 CXD2463R 4) vreset + hpll (sync input) mode when the specified sync signal is externally input to ehd/sync (pin 38), the ext-hd separated from this sync signal is output from hd (pin 36). this signal is input through the shifter to evd (pin 37). at this time, the CXD2463R sync signal is output as shown below based on the amount by which ext-hd is shifted. (the phase can be shifted up to 1/2h with respect to the falling edge of ext-hd.) comp (pin 39) outputs the result of comparing the phase of the falling edge of the shifted ext-hd (signal input to pin 37) and the falling edge of the CXD2463R internal hd. the polarity is compatible with the active filter. ?eia/odd ext-hd (pin 36 output) (1) same phase (2) delayed phase ext-vd (generated inside the CXD2463R) hd (generated inside the CXD2463R) ext-sync (pin 38 input) ? sft-hd (1) to (3) are the signals after shifting ext-hd. 1/2h 1/2h vd (pin 35 output) sft-hd (1) (pin 37 input) sft-hd (2) vd hd sync (3) advanced phase sft-hd (3) vd hd sync sync (pin 25 output)
19 CXD2463R ?eia/even ext-hd (pin 36 output) (1) same phase (2) delayed phase ext-vd (generated inside the CXD2463R) hd (generated inside the CXD2463R) ext-sync (pin 38 input) 1/2h 1/2h vd (pin 35 output) sft-hd (1) (pin 37 input) sft-hd (2) vd hd sync (3) advanced phase sft-hd (3) vd hd sync sync (pin 25 output)
20 CXD2463R ?ccir/odd ext-hd (pin 36 output) (1) same phase (2) delayed phase ext-vd (generated inside the CXD2463R) hd (generated inside the CXD2463R) ext-sync (pin 38 input) 1/2h 1/2h vd (pin 35 output) sft-hd (1) (pin 37 input) sft-hd (2) vd hd sync (3) advanced phase sft-hd (3) vd hd sync sync (pin 25 output)
21 CXD2463R ?ccir/even ext-hd (pin 36 output) (1) same phase (2) delayed phase ext-vd (generated inside the CXD2463R) hd (generated inside the CXD2463R) ext-sync (pin 38 input) 1/2h 1/2h vd (pin 35 output) sft-hd (1) (pin 37 input) sft-hd (2) vd hd sync (3) advanced phase sft-hd (3) vd hd sync sync (pin 25 output)
22 CXD2463R hd field.o field.e vd sync blk v1 v2 v3 v4 510h ccd out 760h ccd out clp1 1 3 2 4 1 3 2 4 492 493 492 493 clp2 9h 20h 494 hd field.e field.o vd sync blk v1 v2 v3 v4 510h ccd out 760h ccd out clp1 491 2 493 492 13 13 2 493 494 clp2 9h 20h timing generator + sync generator block timing chart vertical direction eia (during 510h/760h ccd drive)
23 CXD2463R hd field.e field.o vd sync blk v1 v2 v3 v4 510h ccd out 581 582 583 2 13 7.5h 25h hd field.o field.e vd sync blk 7.5h 25h 1 3 2 4 582 583 v1 v2 v3 v4 510h ccd out clp1 clp2 clp1 clp2 timing generator + sync generator block timing chart vertical direction ccir (during 510h ccd drive)
24 CXD2463R hd field.e field.o vd sync blk v1 v2 v3 v4 760h ccd out 581 582 583 2 13 7.5h 25h hd field.o field.e vd sync blk 7.5h 25h 1 2 582 583 v1 v2 v3 v4 760h ccd out clp1 clp2 clp1 clp2 timing generator + sync generator block timing chart vertical direction ccir (during 760h ccd drive)
25 CXD2463R hd/blk mck (internal clock) h1 h2 rg shp shd v1 v2 v3 v4 sub hsync eq vsync vd clp1 clp2 0 102030405060708090100110 104 mck = 104.88ns 59 79 26 80 94 50 32 62 44 56 26 68 38 72 55 59 14 36 14 14 23 7 timing generator + sync generator block timing chart horizontal direction eia (during 510h ccd drive)
26 CXD2463R hd/blk mck (internal clock) h1 h2 rg shp shd v1 v2 v3 v4 sub hsync eq vsync vd clp1 clp2 0 102030405060708090100110 114 59 84 31 85 99 55 37 67 49 61 31 73 43 77 60 59 14 36 14 14 23 7 mck = 105.61ns timing generator + sync generator block timing chart horizontal direction ccir (during 510h ccd drive)
27 CXD2463R 01020 90 80 140 150 160 170 100 60 50 40 30 70 110 120 130 154 90 40 118 36 12 140 119 76 49 94 67 85 40 103 58 108 85 90 22 56 22 22 hd/blk mck (internal clock) h1 h2 rg shp shd v1 v2 v3 v4 sub hsync eq vsync vd clp1 clp2 mck = 69.84ns timing generator + sync generator block timing chart horizontal direction eia (during 760h ccd drive)
28 CXD2463R 01020 90 80 140 150 160 170 100 60 50 40 30 70 110 120 130 169 90 40 132 36 12 154 84 51 106 73 95 40 117 62 122 95 90 22 56 22 22 hd/blk mck (internal clock) h1 h2 rg shp shd v1 v2 v3 v4 sub hsync eq vsync vd clp1 clp2 mck = 70.48ns 133 timing generator + sync generator block timing chart horizontal direction ccir (during 760h ccd drive)
29 CXD2463R hd e: 2.51 s c: 2.53 s (24ck) v1 odd v2 v3 v4 v1 even v2 v3 v4 e: 1.57 s c: 1.58 s (15ck) e: 1.99 s c: 2.00 s (19ck) e: eia 1ck = 104.88ns c: ccir 1ck = 105.61ns e: 38.38 s c: 38.65 s (366ck) (12ck) e: 1.26 s c: 1.27 s (3ck) e: 0.32 s c: 0.32 s timing generator + sync generator block timing chart charge readout timing field accumulation (during 510h ccd drive)
30 CXD2463R hd e: 2.51 s c: 2.54 s (36ck) v1 odd v2 v3 v4 v1 even v2 v3 v4 e: 2.51 s c: 2.54 s (36ck) e: 2.51 s c: 2.54 s (36ck) e: eia 1ck = 69.84ns c: ccir 1ck = 70.48ns e: 40.56 s c: 40.95 s (581ck) (23ck) e: 1.61 s c: 1.62 s (3ck) e: 0.21 s c: 0.21 s timing generator + sync generator block timing chart charge readout timing field accumulation (during 760h ccd drive)
31 CXD2463R hd 31.78 s (303ck) 1.47 s (14ck) 1/2h eia hsync eq vsync blk (hd) blk (odd) blk (even) vd (even) vd (odd) 6.19 s (59ck) 4.72 s (45ck) 2.30 s (22ck) 4.72 s (45ck) 2.30 s (22ck) 1.47 s (14ck) 1ck = 104.88ns 4.72 s (45ck) 10.90 s (104ck) timing generator + sync generator block timing chart effective horizontal period (during 510h ccd drive)
32 CXD2463R hd 32.00 s (303ck) 1.48 s (14ck) 1/2h ccir hsync eq vsync blk (hd) blk (odd) vd (even) vd (odd) blk (even) 6.23 s (59ck) 4.75 s (45ck) 2.30 s (22ck) 4.75 s (45ck) 2.30 s (22ck) 1.48 s (14ck) 1ck = 105.61ns 4.75 s (45ck) 12.04 s (114ck) timing generator + sync generator block timing chart effective horizontal period (during 510h ccd drive)
33 CXD2463R hd 31.78 s (455ck) 1.54 s (22ck) 1/2h eia hsync eq vsync blk (hd) blk (odd) blk (even) vd (even) vd (odd) 6.29 s (90ck) 4.75 s (68ck) 2.37 s (34ck) 4.75 s (68ck) 2.37 s (34ck) 1.54 s (22ck) 1ck = 69.84ns 4.75 s (68ck) 10.76 s (154ck) timing generator + sync generator block timing chart effective horizontal period (during 760h ccd drive)
34 CXD2463R hd 32.00 s (454ck) 1.55 s (22ck) 1/2h ccir hsync eq vsync blk (hd) blk (odd) vd (even) vd (odd) blk (even) 6.34 s (90ck) 4.79 s (68ck) 2.40 s (34ck) 4.79 s (68ck) 2.40 s (34ck) 1.55 s (22ck) 1ck = 70.48ns 4.79 s (68ck) 11.91 s (169ck) timing generator + sync generator block timing chart effective horizontal period (during 760h ccd drive)
35 CXD2463R h1 h2 rg ccd out mck (internal clock) shp shd high-speed phase timing chart for the timing generator block
36 CXD2463R vsub adj 36k 50k 50k 10k 3.9k 100 +5v 100 10k 10 video out ccd out 10 100k 10k 9.0 to 8.0v +14.55 to +15.45v reset circuit h shifter rg adj 1000p 10p 10k 10k 10k 100k 1000p 1m 0.01 sync in 0.1 1m 1p 39k cxa1310aq CXD2463R 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 25 30 27 24 20 21 29 4 510h/760h black-and-white ccd application circuit ?sync input external synchronization ?electronic iris mode application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
37 CXD2463R sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : solder (0.18) (0.127) 0.18 ?0.03 + 0.08 0.127 ?0.02 +0.05 package outline unit: mm
38 CXD2463R 48pin lqfp (plastic) sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy lqfp-48p-l281 b 1.7max b s s 0.08 ( 8.0 ) 1.4 0.05 a m s 0.07 0.5 9.0 0.2 7.0 0.1 1 12 36 25 37 48 24 13 0.2g b=0.18 0.05 detail b (0.16) (0.125) 0.127 0.02 + 0.05 0.1 0.05 0 ? to 7 ? detail a 0.25 0.6 0.15 p-lqfp48-7x7-0.5 package outline unit: mm amkor
39 CXD2463R sony corporation 48pin lqfp (plastic) sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy lqfp-48p-l282 b 1.7max b s s 0.08 ( 8.0 ) 1.4 0.05 a m s 0.07 0.5 9.0 0.2 7.0 0.1 1 12 36 25 37 48 24 13 0.2g b=0.21 0.05 detail b (0.2) (0.125) 0.127 + 0.05 0.1 0.05 0 ? to 7 ? detail a 0.25 0.6 0.15 p-lqfp48-7x7-0.5 0.02 amkor lead specifications item lead material copper alloy lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.

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